Field of the Invention
One disclosed aspect of the embodiments relates an information processing system which includes a device and a plurality of control units, the device including a circuit capable of configuring a logic circuit according to circuit information.
Description of the Related Art
Programmable logic devices capable of changing an internal logic circuit configuration, such as a complex programmable logic device (CPLD) and a field programmable gate array (FPGA), are known. For example, an FPGA typically includes a fabric and a configuration memory. The fabric includes a plurality of logic blocks and a wiring area between the logic blocks. The FPGA includes an interface for transferring data between an inside and outside of the FPGA. Configuration data (also referred to as circuit information) can be written into the configuration memory to make the fabric (plurality of logic blocks) function as various logic circuits. The writing of circuit information to cause the fabric to function as a logic circuit will be referred to as configuration of the FPGA.
The FPGA fabric can implement various functions by configuration, can thus achieve both the high-speed performance of hardware and the flexibility of software in a compatible manner. Japanese Patent Application Laid-Open No. 2008-287571 discusses a system in which a plurality of central processing units (CPUs) shares a configured FPGA.
Some programmable logic devices include an intellectual property (IP) core (hereinafter, referred to as port) of a bus interface (for example, Peripheral Component Interconnect Express (PCI Express, or PCIe) bus) for achieving high-speed data communication. A CPU connected to the port of such a device can transmit data to be processed by a logic circuit to the device via the port at high speed. If an FPGA including a plurality of such high-speed ports is shared by a plurality of CPUs, each port can be connected with different CPUs. The CPUs can transmit data to the corresponding ports without the intervention of the other CPUs (i.e., independently) and process the data by using logic circuits.
Recent programmable logic devices are capable of performing device configuration from a CPU that transmits circuit information to the devices via the high-speed ports.
Some programmable logic devices may have a port that can receive circuit information from a CPU but does not support configuration using the circuit information. In such a case, a configuration mechanism is needed for a CPU to which no configuration-capable high-speed port is assigned.
In addition, even if a device can be configured from any of a plurality of high-speed ports to which different CPUs are connected, each CPU needs to perform control to avoid conflict with the configuration performed by other CPUs. For example, each CPU needs to perform control to prohibit all the other CPUs from performing configuration.